This invention relates to a system having a processor and a shared resource, and more particularly concerns a technique for preventing a reduction in processing speed at the time of shared resource contention.
For example, in a multiprocessor system constituted by a processor such as a CPU and a DSP (digital signal processor), its processing performance is improved by executing processes in a shared manner between the processor and the DSP. Moreover, by using a memory, a bus, peripheral circuits and the like as shared resources, the chip area can be reduced to achieve low costs.
When, during a data-reading process of the processor toward an external memory, the DSP also issues a data reading process to the same memory to cause an access contention, a bus arbitration circuit controls processes causing the access contention. With respect to the controlling method of the bus arbitration circuit, although a data-reading process from the DSP is accepted, a data-reading process from the DSP is queued until the data reading process from the processor has been completed.
Moreover, in a multiprocessor system that is constituted by a processor and a DSP with the processor conducting a rejecting control process on the DSP, the DSP accepts a processing request from the processor regardless of the state of the DSP; however, when the DSP is executing another process, the DSP does not start the corresponding process immediately, and waits for a while, and upon returning to an executable state, it executes the process in an autonomous manner, and returns the results of the process to the processor side.
However, in the conventional system having a shared resource, in the case when access contention to the shared resource occurs frequently, the number of waiting states until the completion of the preceding process increases, resulting in a reduction in the processing speed in the entire system.
Moreover, the arbitration circuit is only allowed to confirm the state of the shared resource, and is not allowed to confirm the state of the entire system. For example, upon issuance of a processing request from the processor to the DSP while the DSP is executing another process, the conventional arbitration circuit makes the process queued until the preceding process has been completed. Here, since the processor executes the next process in response to the results of the process that has been issued to the DSP, the processor is sometimes set to a waiting state. In such a state, the process that has been issued to the DSP and the processor that is the source of the issuance thereof are maintained in a waiting state until the preceding process has been completed, with the result that the processor and the DSP cannot be used efficiently.
Moreover, in the above-mentioned conventional system having a shared resource, in order to avoid DSP contention in which processing requests to the DSP take place in an overlapped manner, it is necessary to appropriately assign pieces of software to the CPU and the DSP. These assigning processes are carried out manually, resulting in problems in that a great amount of time is required every time a revision in software occurs to cause the subsequent increase in the number of processes.